The present invention relates to a semiconductor integrated circuit; and, more particularly, the invention relates to a technique that is effective when used for generating an internal clock signal, in the case of fetching input data synchronously with an internal clock signal that is generated from an external clock signal.
In a semiconductor integrated circuit including a clock synchronous type memory, in order to fetch data in the memory with reliability, data has to be held only for a predetermined period, and data output control has to be performed. For operation, an internal clock signal having a predetermined phase relation with an external clock has to be generated.
A DDR (Double Data Rate) memory system for transferring data twice in one clock cycle so as to increase the speed of inputting/outputting data of the semiconductor integrated circuit, and an EA (Edge Aligned) data output system, in which the switch phase of a clock signal and that of a data signal are matched in order to enlarge the data window, have been proposed. In such a method, data supplied to an LSI has to be fetched synchronously with an internal clock signal which has a phase that is different from the phase of the clock by almost 90 or 270 degrees (refer to, for example, the following Patent Document).
[Patent Document]
Japanese Unexamined Patent Publication No. Hei 11 (1999)-110062